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  1. Explain about high speed CMOS circuits
  2. What is meant by term snooping
  3. What is meant by the term MESI
  4. What is Cross Talk
  5. What is validation
  6. Who provides the DRC rules
  7. Explain ASIC Design Flow
  8. What is LVS, DRC?
  9. Why is Extraction performed
  10. Explain Custom Design Flow
  11. Explain the Various steps in Synthesis
  12. Why do we use a Clock tree
  13. Explain Clock Skew
  14. Define threshold voltage
  15. What is hot electron effect
  16. What is component binding
  17. Explain the Working of a 2-stage OPAMP
  18. What is 6-T XOR gate
  19. What is FPGA
  20. What is the critical path in a SRAM
  21. Explain sizing of the inverter
  22. How do you detect if two 8-bit signals are same
  23. What is SPICE
  24. What are the differences between IRSIM and SPICE
  25. What is the difference between netlist of HSPICE and Spectre
  26. What are VHDL and Verilog
  27. Explain the difference between write through and write back cache
  28. What is setup time and hold time
  29. Explain the Cross section of a PMOS transistor
  30. Explain the Cross section of an NMOS transistor
  31. What does the above code synthesize to
  32. Explain how MOSFET works
  33. What is the depletion region
  34. How does a pn junction works
  35. What is the doping
  36. What is Channel length modulation
  37. What is the build-in potential
  38. What is Fermi level
  39. What is short Channel effect
  40. How about voltage source
  41. How to improve these parameters
  42. Explain the sizing of the inverter
  43. What is conductance and valence band
  44. What happens if we delay the enabling of Clock signal
  45. What is the difference between Testing & Verification
  46. How can you model a SRAM at RTL Level
  47. What is Latch up? How to avoid Latch up
  48. What is charge sharing
  49. Explain why & how a MOSFET works
  50. Explain CMOS Inverter transfer characteristics
  51. What is Body Effect
  52. Give the expression for CMOS switching power dissipation
  53. How do you size NMOS and PMOS transistors to increase the threshold voltage
  54. Explain the Charge Sharing problem while sampling data from a Bus
  55. Explain the various MOSFET Capacitances & their significance
  56. Explain the working of differential sense amplifier
  57. What happens if we use an Inverter instead of the differential Sense Amplifier
  58. What is Noise Margin and explain the procedure to determine Noise Margin
  59. Why don?t we use just one NMOS or PMOS transistor as a transmission gate
  60. What are early effects and their physical origin
  61. What happens to delay if you increase load capacitance
  62. Explain the working of BJT
  63. What is the ideal input and output resistance of a current source
  64. Give the expression for calculating Delay in CMOS circuit
  65. What are the different limitations in increasing the power supply to reduce delay
  66. What happens to delay if we include a resistance at the output of a CMOS circuit
  67. How does a Band gap Voltage reference work
  68. How does Vbe and Ic change with temperature
  69. What are the two types of noise of MOSFET, how to eliminate them
  70. For a 0.18um and 0.8um technology MOSFET, which has a higher cut-off frequency
  71. Write a pseudo code for sorting the numbers in an array
  72. What happens when the gate oxide is very thin
  73. Explain the Insights of a Tri-State Inverter
  74. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same
  75. Implement an Inverter using a single transistor
  76. What is the different ways of implementing a comparator
  77. What is clock feed through
  78. What are differences between Array and Booth Multipliers
  79. What are the differences between functions and Procedures in VHDL
  80. What is the Implement F = AB+C using CMOS gates
  81. What are the differences between blocking and Non-blocking statements in Verilog
  82. Draw the Layout of an Inverter
  83. Draw the Cross Section of an Inverter
  84. What are the differences between Signals and Variables in VHDL
  85. Explain about stuck at fault models, scan design, BIST and IDDQ testing
  86. What is pipelining and how can we increase throughput using pipelining
  87. How can you construct both PMOS and NMOS on a single substrate
  88. List out the differences between DRAM and SRAM
  89. Explain the operation of a 6T-SRAM cell
  90. Explain Id vs. Vds Characteristics of NMOS and PMOS transistors
  91. Give an Advantages and disadvantages of Mealy and Moore
  92. Explain the working of 4-bit Up/down Counter
  93. Explain various adders and differences between them
  94. What are the Insights of a 4bit adder/Sub Circuit
  95. What is a linked list? Explain the 2 fields in a linked list
  96. What is a D-latch? Write the VHDL Code for it
  97. What are the differences between D-Latch and D flip-flop
  98. What is latchup? Explain the methods used to prevent it
  99. What is the Implement of D flip-flop with a couple of latches
  100. Write a VHDL Code for a D flip-flop
  101. Why do we need both PMOS and NMOS transistors to implement a pass gate
  102. Explain the Insights of an inverter and its working
  103. What neither are the Insights of a 2 input NOR gate. Explain the working
  104. What are the Insights of a 2 input NAND gate Explain the working
  105. Give the various techniques you know to minimize power consumption
  106. What happens if we increase the number of contacts or via from one metal layer
  107. What are the limitations in increasing the power supply to reduce delay
  108. How does Resistance of the metal lines vary with increasing thickness and increasing
  109. What are the ways to Optimize the Performance of a Difference Amplifier
  110. How to find the read failure probability in SRAM
  111. What are set up time and hold time constraints? What do they signify
  112. What transistor level design tools are you proficient
  113. What are the main issues associated with multiprocessor caches
  114. Explain the operation considering a two processor computer system with a cache
  115. For f = AB+CD if B is S-a-1, what are the test vectors needed to detect the fault
  116. In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines
  117. Explain the usage of the shared SPI bus
  118. Implement F= not (AB+CD) using CMOS gates
  119. Implement a 2 I/P and gate using Tran gates
  120. Which gate is normally preferred while implementing circuits using CMOS logic
  121. A circuit has 1 input X and 2 outputs A and B. If X = HIGH for 4 clock ticks, A = 1.
  122. Explain the various steps that are followed to obtain the desirable design
  123. what is the purpose of a processor cache and describe its operation
  124. What will you do if the delay of the combinational circuit is greater than your clock
  125. Implement a function with both rationed & domino of each logic
  126. Implement a function with both merits & demerits of each logic
  127. List the 5 stages of a pipeline
  128. Explain about pipelining
  129. Assuming 1 clock per stage, what is the latency of an instruction in 5 stage machine
  130. What is Fowler-Nordheim Tunnelling
  131. What are the main issues associated with multiprocessor caches and how they can solve
  132. What are the phenomenons which come into play when the devices are scaled
  133. Explain the various Capacitances associated with a transistor and which one of them
  134. In what cases do you need to double clock a signal before presenting it a synchronous
  135. If the current through the poly is 20nA and the contact can take a maximum current
  136. Difference between 80286 and 80287
  137. In a processor these are 120 instructions. Bits needed to implement this instructions
  138. Write an assembly code which can call function in a loop with all value from 0 to 9
  139. Explain the working of a binary counter
  140. Explain RC circuits charging and discharging
  141. Design any FSM in VHDL or Verilog
  142. How do you detect a sequence of "1101" arriving serially from a signal line
  143. Draw a Transmission Gate-based D-Latch
  144. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR
  145. What are the different Adder circuits you studied
  146. Design a divide-by-3 sequential circuit with 50% duty circle
  147. Give a circuit to divide frequency of clock cycle by two
  148. Given a circuit, draw its exact timing response
  149. Give two ways of converting a two input NAND gate to an inverter
  150. What is PSW
  151. What is the difference between MOV and MVI
  152. What do you mean by wait state? What is its need?
  153. What happens during DMA transfer
  154. What is an interrupt
  155. What are the different flags in 8085
  156. What is the immediate addressing mode
  157. What are the functions of RIM, SIM, IN
  158. What are the different addressing modes in 8085
  159. What does it mean by embedded system
  160. What is the function of accumulator
  161. What is flag, bus
  162. Why is data bus bi-directional
  163. Why are program counter and stack pointer 16-bit registers
  164. How many bit microprocessors are their in 8085
  165. Which type of architecture 8085 has
  166. What is a program counter? What is its use
  167. Which line will be activated when an output device require attention from CPU
  168. In 8085 microprocessor READY signal does.which offollowing is incorrect statemen
  169. How many memory locations can be addressed by a microprocessor with 14 address lines
  170. What are tri-state devices and why they are essential in a bus oriented system
  171. Give the truth table for a Half Adder and give a gate level implementation of same
  172. What is ALE
  173. Explain the functions of ALE in 8085
  174. What are set up time & hold time constraints
  175. What do they signify which one is critical for estimating maximum clock frequency